In recent years, thin film transistor liquid crystal display (TFT-LCD) devices have been rapidly developed and play a dominant position in flat display market due to their characteristics of small volume, low power consumption, no radiation and the like.
The fabricating process of TFT-LCDs includes a step of assembling a fabricated array substrate and a fabricated color filter substrate together by using a sealant, so as to form a display panel. After the formation of the display panel, various tests are performed on the display panel, including performing test on the display panel by using a display panel test structure.
FIG. 1 is a diagram illustrating a display panel test structure in the prior art. FIG. 1 shows a display area Q1 and a lead area Q2 of a display panel, the lead area Q2 being located at a peripheral area of the display area Q1. As shown in FIG. 1, a plurality of gate lines 20 and a plurality of data lines 10, which are intersected with each other, are provided in the display area Q1. In a case where the display panel is a single-side-driving display panel, both an end of each gate line 20 and an end of each data line 10 extend from the display area Q1 into the lead area Q2, so that signals can be loaded to the gate lines 20 and the data lines 10. In this case, before inputting display signals to the gate lines 20 and the data lines 10, the condition of the gate lines 20 and the data lines 10 has to be tested, so that whether these signal lines are defective can be determined.
As an example, a display panel test structure for testing whether the data lines 10 are defective will be described below. Referring to FIG. 1, the display panel test structure for testing whether the data lines 10 are defective generally includes shorting bars 30, which are arranged in a test area Q3. The test area Q3 is arranged in a peripheral area of the lead area Q2 of the display panel. For a single display panel, a structure called 6D Shorting Bar is generally employed, in which the data lines 10 are divided into six groups, in each of which the data lines 10 are short-circuited together through a shorting bar 30. In a test procedure, a plurality of block pins (test probes) contact a plurality of data lines 10 in the lead area Q2, respectively, i.e., a block pin contacts a data line 10 corresponding thereto, so that signals are loaded to the respective data lines 10. By such arrangement, even in a case where an individual block pin experiences a situation called Pin-miss (i.e., a situation in which some block pin fails to contact a data line 10 corresponding thereto, resulting in that signals cannot be loaded to said data line 10), since data lines 10 in a same group are short-circuited together through a shorting bar 30, the pin-missed data line 10 can be loaded with signals through other data lines 10 short-circuited therewith and from the same group. Therefore, it is possible to ensure that defective of each data line 10 can be detected.
However, the inventors have found at least the following defects existing in the prior art, including: (1), in the dot-inversion or line-inversion mode, polarities of driving voltages of two adjacent data lines 10 are opposite to each other, and in this case, once two adjacent block pins are short-circuited, an excessive current will be produced, burning down the data lines 10 or causing abnormalities of signal loading; and (2), a large number of small block pins are employed, so that data lines 10 on the display panel may be scratched when contacting block pins.